Hardware Support For Serializable Transactions: A Study of Feasibility and Performance

The conflict-serializability consistency model can reduce abort rates and improve performance in software transactional memory (TM) systems. We discuss how this model can be supported on hardware-based TM systems. We consider a hybrid implementation where serializability is implemented as a software layer on top of a base hardware TM system. We also extend the base hardware TM system to fully support serializability in hardware with minimal compiler support. We implement and evaluate the hybrid system and an ideal version of the full hardware system. Our evaluation using two typical benchmarks shows that support for serializability in hardware-based TM systems results in reduced conflicts. However, the overhead of software in the hybrid implementation eliminates any benefits; performance is 2-5 times slower compared to the base hardware system. In contrast, the ideal hardware system improves performance by up to 23.2%, because of the reduction in the aborts. We conclude that with efficient implementations in hardware, conflict-serializability can improve performance, especially for applications with high cost of aborts.